A chip-on-chip structure obtained by opposing and bonding the surface of a semiconductor chip to the surface of another semiconductor chip, for example, is known as a structure for attaining downsizing and improvement in integration of a semiconductor device.
In the semiconductor device of the chip-on-chip structure, large numbers of functional bumps and connection confirmation bumps are provided on the surface of each semiconductor chip. On the surface of each semiconductor chip, for example, a large number of functional bumps are arranged at the center thereof in the form of a lattice, and connection confirmation bumps are arranged on the four corners.
In each semiconductor chip, all functional bumps are formed with the same height (projection amount from the surface of the semiconductor chip) with a metallic material such as copper (Cu). The tip end of each functional bump of one semiconductor chip is provided with a solder bond alloyable with the material of the functional bump. Each functional bump of the one semiconductor chip and each functional bump of the other semiconductor chip are connected with each other through this solder bond, thereby attaining electrical and mechanical connection between the semiconductor chips.
On the other hand, the connection confirmation bumps are formed at the same height (projection amount from the surface of the semiconductor chip) as the functional bumps with the same metallic material as the functional bumps in each semiconductor chip. The tip end of each connection confirmation bump of the one semiconductor chip is provided with a solder bond. When both the semiconductor chips are parallelly bonded to each other, therefore, each connection confirmation bump of the one semiconductor chip and each connection confirmation bump of the other semiconductor chip are connected with each other through the solder bond. Therefore, whether or not both the semiconductor chips are parallelly connected with each other can be determined by checking the connection state between these corresponding connection confirmation bumps. In other words, both the semiconductor chips can be determined as parallelly bonded to each other if the connection states between all corresponding connection confirmation bumps are excellent. If even one of the connection states between the corresponding connection confirmation bumps is defective, on the other hand, both the semiconductor chips can be determined as not parallelly bonded to each other (the one semiconductor chip is bonded to the other semiconductor chip in an inclined manner).
Patent Document 1: Japanese Unexamined Patent Publication No. 08-153747